UDEMY FPGA VHDL Course Coding QSPI nor Flash Memory BOOKWARE-iLEARN

iLEARN
source: https://www.udemy.com/course/fpga-vhdl-coding-qspi-nor-flash-memory-from-zero-to-hero/
looking for locations in:
10 GBit .SE
10 GBit .NO
and other european locations

41M	1. Introduction.mp4
223M	10. Writing the controller for the QSPI PART1.mp4
103M	11. Write the Read Data Process.mp4
115M	12. Writing the Write enable to the global clock.mp4
229M	13. Write the Send Quad command Process.mp4
130M	14. Write the Send Quad Address Process.mp4
106M	15. Write the Send Quad Data Process.mp4
119M	16. Write the Send NonVolatile Data Process.mp4
319M	17. Write the Main State Machine.mp4
463M	18. Write the Initialization State Machine.mp4
329M	19. Write the Read status register state machine.mp4
25M	2. Nor flash memory Vs Nand flash memory.mp4
342M	20. Write the Fast Read state machine.mp4
268M	21. Write the Data to the QSPI state machine.mp4
91M	22. Write 16 bits command state machine.mp4
138M	23. Write 8 bits command state machine.mp4
100M	24. Write the Sector Erase state machine.mp4
227M	25. Connecting the QSPI controller and the register file to the top entity.mp4
261M	26. Adding the QSPI flash memory Verilog component to the test bench.mp4
187M	27. Open the project files in Modelsim and fixing syntax errors.mp4
793M	28. Simulate the project and fix the clocks and initialization.mp4
676M	29. Writing the Testbench and test the Read status register.mp4
57M	3. SPI Protocol and our Flash.mp4
738M	30. Writing the Testbench and test the Write data to the QSPI.mp4
515M	31. Writing the Testbench and test the Fast read.mp4
547M	32. Writing the Testbench and test the Write 16 bits.mp4
340M	33. Writing the Testbench and test the Write 8 bits.mp4
223M	34. Writing the Testbench and test the Sector erase.mp4
42M	35. Final files for this Course and Conclusions!.mp4
27M	36. Bonus lecture.mp4
43M	4. Download the QSPI component Verilog model.mp4
284M	5. Our QSPI Nor flash memory PDF datasheet explained.mp4
196M	6. QSPI nor flash communication timing.mp4
295M	7. VHDL Code Plan - Must watch to understand the rest!.mp4
211M	8. Writing the top entity and the Testbench Part1.mp4
286M	9. Write the Registers File Component.mp4
8.9G	total